Advances in semiconductor manufacturing technologies have resulted in dramatically increased circuit packing densities and higher speeds of operation. In order to achieve such increased densities, a wide variety of evolutionary changes have taken place with respect to semiconductor processing techniques and semiconductor device structures over the years.
Many of these process and structural changes have been introduced in connection with device scaling, in which ever smaller device geometries have been achieved. One consequence of conventional FET device scaling is a requirement to reduce operating voltages. The reduced operating voltages are required, at least in part, because conventional FET device scaling needs a thinner gate dielectric layer in order to produce the desired electrical characteristics in the scaled-down transistor. Without a reduction in operating voltage, the electric field impressed across the thinner gate dielectric during circuit operation can be high enough for dielectric breakdown to become a problem.
A common goal of all integrated circuit designs is to reduce the footprint (e.g., the amount of space) that the circuit occupies. Integrated circuits with reduced footprints can help to make the overall size of an electronic device smaller, or can allow for more integrated circuits to be contained within a device while maintaining the size of the device. However, the goal of reducing the footprint of a particular device can stand in tension with other design goals and needs pertinent to semiconductor devices.
It is noted that the drawn representations of various semiconductor structures shown in the figures are not necessarily drawn to scale, but rather, as is the practice in this field, drawn to promote a clear understanding of the structures and process steps which they are illustrating.